Current processor and memory technologies face design challenges that are related to the continuous scaling down of the minimum feature size according to Moore's Law. Moreover, the conventional computing architecture is no longer an effective way to fulfill the demands of modern applications. An exigent need therefore exists to shift to new technologies at both architectural and device levels. Recently, the high-density memristor crossbar architecture attracted attention in this regard. Memristor based resistive RAM is a promising candidate to replace HDD, DRAM, and flash memories. Moreover, the high-density memristive crossbar is also a perfect candidate for neural bio-inspired computing. Such applications are driven by recent advances in the fabrication of memristive devices.
The main advantage of a redox memristive array is its very high density, which entails each memory cell occupying only a few nanometers. The array is simply built as a crossbar structure. This simple assembly is inherently self-aligned and can be fabricated using only one or two lithography masks. While the simplicity of the structure is its principal advantage, it is also the source of its main problem, namely the sneak-paths problem. While accessing the array, current should flow through the desired cell only. However, nothing in the crossbar prevents the current from sneaking through other cells in the array as shown in FIGS. 1A and 1B, which illustrate the desired current path 102 and the sneak-paths 104. This parasitic current ruins the reading and writing operations and adds a considerable amount of undesired power consumption.
The direct solution to the sneak-paths problem is to add a selector (gate) to each memory cell, such as MOS transistors, threshold devices, or complementary memristors. In general, doing so comes at the expense of array density and the complexity of the fabrication process (low cost per bit). As a result, the need arises to address the sneak-paths challenge using the typical gateless crossbar structure in a similar quality of the gated arrays. Several techniques have been proposed for handling such an effect in gateless arrays, including multistage readout, multiport readout, unfolded arrays, engineering device nonlinearity, and grounded array. However, these techniques either require extended accessing time, rely on a power-hungry accessing, reduce the density of the array significantly, or are simply not valid solutions for practical size arrays.